From dc6be85831c71d2d8d26753465db064eeba6d6d4 Mon Sep 17 00:00:00 2001 From: "djm@kirby.fc.hp.com" Date: Mon, 6 Jun 2005 18:05:03 +0000 Subject: [PATCH] bitkeeper revision 1.1668.1.2 (42a4904fwO30IinqLPqfFaI7md-pLA) Merge corrections --- xen/arch/ia64/domain.c | 2 +- xen/arch/ia64/hyperprivop.S | 4 ++-- xen/arch/ia64/privop.c | 2 +- xen/arch/ia64/regionreg.c | 12 +++++------- 4 files changed, 9 insertions(+), 11 deletions(-) diff --git a/xen/arch/ia64/domain.c b/xen/arch/ia64/domain.c index 28ddf0b94b..c6e622c8d7 100644 --- a/xen/arch/ia64/domain.c +++ b/xen/arch/ia64/domain.c @@ -257,7 +257,7 @@ void arch_do_createdomain(struct vcpu *v) d->xen_vaend = 0xf300000000000000; d->shared_info_va = 0xf100000000000000; d->arch.breakimm = 0x1000; - ed->arch.breakimm = d->arch.breakimm; + v->arch.breakimm = d->arch.breakimm; // stay on kernel stack because may get interrupts! // ia64_ret_from_clone (which b0 gets in new_thread) switches // to user stack diff --git a/xen/arch/ia64/hyperprivop.S b/xen/arch/ia64/hyperprivop.S index cbb8b39e4c..ae79ab070c 100644 --- a/xen/arch/ia64/hyperprivop.S +++ b/xen/arch/ia64/hyperprivop.S @@ -90,7 +90,7 @@ GLOBAL_ENTRY(fast_break_reflect) mov cr.ipsr=r20;; // save ipsr in shared_info, vipsr.cpl==(ipsr.cpl==3)?3:0 cmp.ne p7,p0=3,r21;; -(p7) mov r21=r0 +(p7) mov r21=r0 ;; dep r20=r21,r20,IA64_PSR_CPL0_BIT,2 ;; dep r20=r23,r20,IA64_PSR_RI_BIT,2 ;; // vipsr.i=vpsr.i @@ -110,7 +110,7 @@ GLOBAL_ENTRY(fast_break_reflect) // save ifs in shared_info adds r21=XSI_INCOMPL_REG_OFS-XSI_PSR_IC_OFS,r18 ;; st4 [r21]=r0 ;; - adds r21=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 + adds r21=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;; st8 [r21]=r0 ;; cover ;; mov r20=cr.ifs;; diff --git a/xen/arch/ia64/privop.c b/xen/arch/ia64/privop.c index 6737d51446..1f50ea2448 100644 --- a/xen/arch/ia64/privop.c +++ b/xen/arch/ia64/privop.c @@ -795,7 +795,7 @@ ia64_hyperprivop(unsigned long iim, REGS *regs) (void)priv_itc_i(v,inst); return 1; case HYPERPRIVOP_SSM_I: - (void)vcpu_set_psr_i(ed); + (void)vcpu_set_psr_i(v); return 1; } return 0; diff --git a/xen/arch/ia64/regionreg.c b/xen/arch/ia64/regionreg.c index cea0d6891e..6653d4b6a8 100644 --- a/xen/arch/ia64/regionreg.c +++ b/xen/arch/ia64/regionreg.c @@ -287,7 +287,7 @@ int set_one_rr(unsigned long rr, unsigned long val) if (rreg == 6) newrrv.ve = VHPT_ENABLED_REGION_7; else newrrv.ve = VHPT_ENABLED_REGION_0_TO_6; newrrv.ps = PAGE_SHIFT; - if (rreg == 0) ed->arch.metaphysical_saved_rr0 = newrrv.rrval; + if (rreg == 0) v->arch.metaphysical_saved_rr0 = newrrv.rrval; set_rr(rr,newrrv.rrval); } return 1; @@ -296,11 +296,11 @@ int set_one_rr(unsigned long rr, unsigned long val) // set rr0 to the passed rid (for metaphysical mode so don't use domain offset int set_metaphysical_rr0(void) { - struct exec_domain *ed = current; + struct vcpu *v = current; ia64_rr rrv; // rrv.ve = 1; FIXME: TURN ME BACK ON WHEN VHPT IS WORKING - set_rr(0,ed->arch.metaphysical_rr0); + set_rr(0,v->arch.metaphysical_rr0); } // validates/changes region registers 0-6 in the currently executing domain @@ -325,8 +325,7 @@ void init_all_rr(struct vcpu *v) ia64_rr rrv; rrv.rrval = 0; - rrv.rid = v->domain->metaphysical_rid; - rrv.rrval = ed->domain->arch.metaphysical_rr0; + rrv.rrval = v->domain->arch.metaphysical_rr0; rrv.ps = PAGE_SHIFT; rrv.ve = 1; if (!v->vcpu_info) { printf("Stopping in init_all_rr\n"); dummy(); } @@ -380,9 +379,8 @@ unsigned long load_region_regs(struct vcpu *v) ia64_rr rrv; rrv.rrval = 0; - rrv.rid = v->domain->metaphysical_rid; + rrv.rid = v->domain->arch.metaphysical_rr0; rrv.ps = PAGE_SHIFT; - rrv.rrval = v->domain->arch.metaphysical_rr0; rrv.ve = 1; rr0 = rrv.rrval; set_rr_no_srlz(0x0000000000000000L, rr0); -- 2.30.2